1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method of the same. More particularly, the present invention relates to a semiconductor device including a MOS (Metal Oxide Semiconductor) transistor with its active region having an entirely rounded surface, and a manufacturing method of the same.
2. Description of the Background Art
FIG. 21 shows an example of the cross-sectional structure of a conventional MOS transistor. As shown in the figure, an isolation oxide film 5 is selectively formed at the main surface of a semiconductor substrate 1. A gate electrode 9 is formed on an active region 11 located between the isolation oxide films 5, with an oxide film 8 interposed therebetween.
Hereinafter, a method for manufacturing the MOS transistor of FIG. 21 will be described with reference to FIGS. 22 and 23. FIGS. 22 and 23 are cross-sectional views showing characteristic first and second steps of the manufacturing process of the aforementioned MOS transistor.
First, a mask film (not shown) is formed on the main surface of the semiconductor substrate 1. Oxidation is conducted using the mask film so as to form the isolation oxide film 5 as shown in FIG. 22. Then, as shown in FIG. 22, an oxide film 7 for preventing damage upon ion implantation is formed, and ion implantation for forming the MOS transistor is conducted.
Thereafter, as shown in FIG. 23, the oxide film 7 used in the ion implantation is removed by wet etching using HF or the like. At this time, the isolation oxide film 5 is also etched, whereby a recessed portion 12 is produced.
Then, as shown in FIG. 21, the oxide film 8 serving as a gate oxide film of the MOS transistor, and the gate electrode 9 are formed.
Hereinafter, another conventional example will be described with reference to FIGS. 24A, 24B to 26A, 26B. FIGS. 24A and 24B are cross-sectional views of an access MOS transistor portion and a driver MOS transistor portion in a memory cell of a conventional SRAM (Static Random Access Memory), respectively.
In general, the SRAM memory cell is required to have a large current ratio of the driver MOS transistor to the access MOS transistor in order to stabilize the cell operation. It is more desirable that the access MOS transistor has a smaller current value and the driver MOS transistor has a larger current value.
Accordingly, the width Wd of an active region 11 of the driver MOS transistor is larger than the width Wa of an active region 11 of the access MOS transistor, and the gate length Ld of the driver MOS transistor is shorter than the gate length La of the access MOS transistor.
The SRAM memory cell transistor is also required to have the following characteristics. It is more desirable that the access MOS transistor has a lower threshold voltage Vth upon back biasing. Moreover, because of the longer gate length of the access MOS transistor, it is preferable that the access MOS transistor is subjected to channel doping at low energy, which suppresses the back bias effect.
On the other hand, because of the shorter gate length of the driver MOS transistor, it is preferable that the driver MOS transistor is subjected to channel doping at high energy in order to suppress a punch-through.
Hereinafter, a method for manufacturing the SRAM memory cell of FIGS. 24A and 24B will be described. FIGS. 25A, 25B and FIGS. 26A, 26B are cross-sectional views showing characteristic first and second steps of the manufacturing process of the SRAM memory cell shown in FIGS. 24A and 24B.
As in the case of the aforementioned MOS transistor, a mask film is formed on the semiconductor substrate 1, and oxidation is conducted using this mask film. Thus, an isolation oxide film 5 is formed as shown in FIGS. 25A and 25B.
Then, as shown in FIGS. 25A and 25B, an oxide film 7 for preventing damage upon ion implantation is formed, and ion implantation for forming the access MOS transistor and the driver MOS transistor is conducted.
The oxide film 7 has the same thickness both in the portion where the access MOS transistor is to be formed and in the portion where the driver MOS transistor is to be formed (hereinafter, such portions are respectively referred to as access MOS transistor formation portion and driver MOS transistor formation portion).
Thereafter, as shown in FIGS. 26A and 26B, the oxide film 7 is removed by wet etching using HF or the like. Then, as shown in FIGS. 24A and 24B, an oxide film 8 serving as a gate oxide film of the access MOS transistor and the driver MOS transistor, and a gate electrode 9 are formed.
As described above, the MOS transistor of FIG. 21 has the recessed portion 12 produced at the edge of the isolation oxide film 5, which causes a leak current in the MOS transistor. This problem may also occur in the example of FIGS. 24A and 24B.
As described above, the oxide film 7 for channel implantation has the same thickness both in the access MOS transistor and the driver MOS transistor shown in FIGS. 24A and 24B. Therefore, it has been impossible to make the respective depths of the channel doping regions of the access MOS transistor and the driver MOS transistor different from each other, unless, for example, a mask film is formed to cover one of the respective regions where the access MOS transistor and the driver MOS transistor are to be formed.
Moreover, it has been impossible to make the respective thicknesses of the gate insulating films of the access MOS transistor and the driver MOS transistor different from each other without adding the step of forming an insulating film.
In other words, it has been difficult to improve the memory cell performance of the SRAM as well as stabilize the memory cell operation thereof without conducting any additional step.